The disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a semiconductor device in which channels are formed in a vertical direction and to a method of fabricating such device.
As semiconductor device integrity increases, a semiconductor device with channels formed in an up and down direction relative to the substrate of the device (referred to herein as vertical channels), and capable of implementing a configuration of 4F2, has been known to the inventors as one method of improving cell efficiency.
FIG. 1 is a schematic cross-sectional view of a known conventional semiconductor device with vertical channels.
Referring to FIG. 1, the known semiconductor device includes a substrate 10, a pillar pattern having a pillar head 11 and a pillar neck 12, a gate hard mask layer 13 for protecting an upper portion of the pillar pattern, a sidewall protection layer 14 for protecting a sidewall of the pillar head 11, a gate insulation layer 15 surrounding the pillar neck 12 and a gate electrode 16. Furthermore, source and drain regions may be formed on the substrate 10 and the pillar head 11, and a vertical channel may be formed in the pillar neck 12 to selectively connect the regions.
However, since a diameter of the pillar neck 12 is smaller than a diameter of the pillar head 11 and a gate hard mask layer 13 is placed over the pillar head 11 in the above configuration of the pillar pattern, it is potential that a pillar pattern may leans over or adheres to another pillar pattern, as shown in FIG. 2.
Also, since the pillar head 11 and pillar neck 12 are formed by etching without an etch stop layer, it is potential that the heights of respective pillar patterns are not even such as H1<H2. This results in different channel lengths in different pillar patterns, as shown in FIG. 3.
In addition, when a conductive layer is filled in the space between adjacent pillar patterns in order to later form the gate electrode 16, voids 21 and seams are potentially formed inside the conductive layer due to a high aspect ratio between the pillar patterns, as shown in FIG. 4. When a process of patterning the conductive layer is performed later, the gate insulation layer 15 and the substrate 10 are potentially punched through (see 22 of FIG. 5) due to different etching speeds originating from the presence of the aforementioned voids 21 and seams. Furthermore, the sidewall protection layer 14 is possibly lost excessively due to an inappropriate etching selection ratio during the conductive layer patterning process, which attacks the pillar head 11, as shown in FIG. 6 (see 23 of FIG. 6).